1. Field of the Invention
The invention relates to the area of data communication, and particularly, to techniques and an arbitration device for accessing a memory device.
2. Description of Related Art
A typical system-on-chip (SoC) has various function modules, such as processors and hardware accelerators, which may be required to access a memory. The memory includes an external memory, for example, an SDRAM (Synchronous Dynamic Random Access Memory), a DDR memory, and an NOR memory, and may also include a shared memory on chip such as ROM, SRAM (Static Random Access Memory) for facilitating communication among the function modules.
A processor and other function modules work independently and access the memory respectively based on their own demands. Thus, each memory may be accessed by several function modules. However, a typical high-capacity memory can be accessed by only one of the function modules at a time. The access to the memory should be carried out by a bus arbitration device that dictates which one of the function modules can access the memory according to a set of certain criteria and in the meantime temporarily suspends access requests by other function modules until the access of the present function module is completed.
A conventional system for accessing the memory shown in FIG. 1 includes N function modules, a bus arbitration device, a plurality of types of memories, and N buses connecting the bus arbitration device to the N function modules. All function modules rely on an independent bus arbitration device to be granted the access permission at a certain time. Each of the function modules is given a predetermined priority. The bus arbitration device chooses to grant a function module with the highest priority the access permission according to the predetermined priority of each of the function modules, and then switches a bus of the memory to the bus corresponding to the function module obtaining the access permission.
The bus arbitration device in a conventional design compares the priorities of these function modules through a tree comparator, outputs a serial number of the function module having the highest priority, and then drives a multi-selector to select one of buses to a memory according to the serial number of the function module so as to switch the bus of the memory to the bus of the function module that has the highest priority.
A principle of the operation of the tree comparator can be understood in following description. The priorities of every two neighboring function modules in a first stage are compared with each other, by which N/2 comparing results can be obtained. The function modules with higher priority corresponding to the N/2 results are classified to a second stage. The priorities of every two neighboring function modules in the second stage are compared with each other, by which N/4 results can be obtained. The function modules corresponding to the N/4 results are classified to a third stage. The rest function module can be compared in the same manner until only one result is obtained, i.e., the serial number of the function module with the highest priority is obtained. Thus, log 2N may be the stage number of the tree comparator. At least one exclusive-OR gate is necessary at each stage of the tree comparator. Thus, signals may undergo delays at least log 2N exclusive-OR gates. The function module with the highest priority functions as a selecting end of the multi-selector while the buses corresponding to the function modules function as inputs of the multi-selector. The bus of the memory functions as an output of the multi-selector. The multi-selector switches the bus of the memory to that of the function module with the highest priority, according to the serial number of the function module selected by the multi-selector.
In a complicated SoC, there could be many of the function modules that need to perform parallel operations. With the frequency of a system becoming increasingly high, the requirements on an arbitration switching circuit become higher with so many function modules. For example, the delay of the arbitration switching circuit should be limited within 8 ns when the frequency of the clock of the bus is higher than 125 MHz. The number N in the prior arts is typically larger than 16. However, when the stage number of the tree comparator is greater than 5, it is difficult to limit the delay of the arbitration switching circuit within 8 ns. Thus, improvement of the speed of the arbitration switching circuit is highly desired although the difficulty in design is known in a system with many function modules running at high speeds.
In brief, one problem needed to be solved is to minimize the delay of the arbitration switching circuit and increase the operation speed of the arbitration switching circuit so as to enable the arbitration switching circuit to be widely applied to various SoC chips and satisfy requirements under various conditions.